Research Areas

Work spans transistor-level memory primitives, open-source processor microarchitectures, and quantum machine learning frameworks.

2025 · active

In-Memory Computing

In-memory computing (IMC) represents a paradigm shift in computer architecture by performing computations directly within memory arrays, eliminating costly data movement between memory and processing units. Our research focuses on developing efficient IMC architectures for machine learning inference workloads such as CNN, LLM, etc. Exploring both analog and digital implementations using CMOS-silicon DRAM/SRAM memories as well as emerging non-volatile memory technologies such as ReRAM, PCM, and MRAM.

Digital SRAM In-Memory Computing
Programmable Mixed-Signal SRAM In-Memory Computing
ADC/DAC-free In-Memory Computing
ReRAM-based In-Memory Computing

Code

2025 · active

RISC-V Architectures

RISC-V is an open-source instruction set architecture that enables innovation in processor design. Our lab develops custom RISC-V cores with specialized extensions for various application domains, including edge AI. We also contribute to the RISC-V ecosystem through tools, simulators, and educational resources. We also explore superscalar and out-of-order execution models along with vector and matrix processors to enhance performance.

Custom RISC-V core implementations
Vector and matrix extension development
Open-source processor development

Code

2025 · active

Hardware Accelerators

Domain-specific hardware accelerators provide orders of magnitude improvement in performance and energy efficiency compared to general-purpose processors. Our research develops accelerator architectures for applications like LLM training and inference, drawing inspiration from designs like Gemmini and Eyeriss. We explore novel dataflow architectures, including systolic arrays, memory hierarchies, and interconnects to optimize throughput and minimize latency.

Deep learning accelerator architectures
Systolic array designs
Interconnects
Hardware-software co-design
Compiler optimizations for accelerators

Code

2025 · active

Quantum Computing

Quantum computing represents a new computing paradigm that exploits quantum mechanics principles such as superposition and entanglement to perform information processing beyond classical limits. Our research focuses on the design and simulation of quantum circuits and algorithms, with particular emphasis on quantum machine learning techniques for accelerating classical ML workloads and circuit-level approaches toward quantum AI accelerators.

Quantum circuits and gate level design
Quantum machine learning for classical ML acceleration
Quantum AI and accelerator-oriented circuit design

2026 · active

Edge AI

Our Edge AI research develops architectures, runtimes, and compiler strategies for deploying AI models under strict constraints in power, latency, and memory. We investigate quantization-aware pipelines, sparsity-aware execution, and accelerator-friendly model transformations to support robust on-device intelligence for sensing, robotics, and embedded systems.

TinyML and on-device inference
Model compression and quantization
Edge-aware accelerator co-design
Compiler and runtime optimizations

2026 · active

Photonics

Photonics-based computing offers the potential for ultra-high bandwidth and improved energy efficiency for selected compute kernels. Our work studies photonic building blocks, architecture-level integration strategies, and system-level co-design to identify where photonics can accelerate next-generation AI, communication, and sensing workloads.

Photonic compute primitives
Electro-photonic co-design
High-bandwidth interconnects
AI acceleration using photonic pathways